1. Field of the Invention
The present invention relates to a technology for analyzing a circuit delay.
2. Description of the Related Art
Recently, influence of statistical factors, such as dispersion in processing, in manufacturing of a very large scale integration (VLSI) has become stronger because the processing has become finer. Similarly, in VLSI designing, a delay improving technique in which the influence is taken into account in advance is necessary to create a circuit having a desired performance at a high yield. Conventionally, as a method of eliminating an unnecessary delay margin, taking the processing dispersion into account, a statistical delay analysis has been proposed (for example, Japanese Patent Application Laid-Open Publication No. 2004-252831). A delay minimizing apparatus that minimizes a delay of a logic circuit has also been proposed (for example, Japanese Patent Application Laid-Open Publication No. H7-334530).
However, with the conventional delay improving technique, it is difficult to accurately handle the statistical factors. For example, when the statistical factors are handled in a conventional static delay analysis (STA), a very pessimistic and incorrect circuit delay value is obtained because the estimation is executed based on the worst values of the factors. Therefore, the circuit designing is required to be redone, resulting in increase of the load on design engineers and increase of the design period.
Moreover, because the delay analysis is executed on each of all paths in a chip, the processing time required for the delay analysis is tremendous. As a result, the design period increases. Furthermore, because the above conventional technique is a technique called “partial collapsing” that reduces the circuit delay at a logic level, the circuit delay is minimized without executing the timing analyses. Therefore, a delay in a critical path is not taken into account, and an accurate circuit delay can not be obtained.